Static random access memory with write assist circuit

A device, comprising:

• a memory array with first memory cells coupled to first bitlines and second memory cells coupled to second bitlines;
• and
• a voltage generator circuit configured to:
• couple, via a first capacitive element, a reference voltage to a first negative voltage applied to the first bitlines located at a first distance from the first capacitive element, in response to first row address information associated with the first memory cells being accessed;
• and
• couple, via the first capacitive element and a second capacitive element, the reference voltage to a second negative voltage applied to the second bitlines located at a second distance from the first capacitive element, in response to second row address information associated with the second memory cells being accessed,
• wherein the second distance is greater than the first distance, and
• wherein the second negative voltage is lower than the first negative voltage.

A method, comprising:

• controlling a reference voltage provided to a first bitline electrically coupled to a first memory cell and a second bitline electrically coupled to a second memory cell, wherein the second bitline is longer than the first bitline;
• coupling the reference voltage to a first negative voltage with a first capacitive element, in response to first row address information associated with the first memory cell being accessed, wherein the first negative voltage is applied to the first bitline coupled to the first memory cell, and wherein the first memory cell is located at a first distance from the first capacitive element;
• and
• coupling the reference voltage to a second negative voltage with the first capacitive element and a second capacitive element, in response to second row address information associated with the second memory cell being accessed, wherein the second memory cell is located at a second distance from the first capacitive element,
• wherein the second distance is greater than the first distance, and
• wherein the second negative voltage is lower than the first negative voltage and is applied to the second bitline coupled to the second memory cell.