Memory device having load offset mismatch compensation
AssigneeSamsung Electronics Co., Ltd.
InventorsMi Ji Jang, Young Hun Seo
Life of this patent
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Abstract
A memory device including a memory cell array which includes a plurality of memory cells connected to each of a plurality of bit lines and word lines, a first bit line sense amplifier electrically connected to a first bit line through a first memory cell and a first connecting wiring and a second bit line sense amplifier electrically connected to a second bit line through a second connecting wiring having a length different from that of the first connecting wiring. A first compensation load of the first bit line and a second compensation load of the second bit line are adjusted to equalize RC loads of the first bit line and the second bit line.
Claims12
A memory device comprising:
- a memory cell array including a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines;
- a first bit line sense amplifier electrically connected to a first memory cell from among the plurality of memory cells through a first bit line from among the plurality of bit lines and a first connecting wiring having a first length;
- a first offset compensation transistor electrically connected to the first bit line and the first bit line sense amplifier;
- a second bit line sense amplifier electrically connected to a second memory cell from among the plurality of memory cells through a second bit line from among the plurality of bit lines and a second connecting wiring having a second length different than the first length;
- and
- a second offset compensation transistor electrically connected to the second bit line and the second bit line sense amplifier,
- wherein the first bit line includes a first compensation load and the second bit line includes a second compensation load to equalize RC loads of the first bit line and the second bit line.
Dependencies are inferred from the claim text.