Memory array circuit

A memory array circuit, comprising:

• a semiconductor substrate with an original surface;
• an access transistor formed within a first active region of the semiconductor substrate;
• a capacitor connected to a source region of the access transistor;
• a memory array;
• a bit line electrically connected to a drain region of the access transistor through a first plug under the original surface and further connected to the memory array;
• and
• a bit line sense amplifier circuit connected to the bit line, comprising:
• a first plurality of transistors, each transistor comprising a gate node, a first conductive node, and a second conductive node;
• a plurality of switch layers;
• and
• a first set of connection lines electrically connecting the first plurality of transistors to the bit line, wherein the plurality of switch layers electrically connect the first set of connection lines to the bit line and the complementary bit line;
• wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line is under the original surface of the semiconductor substrate and extends from the memory array to the bit line sense amplifier circuit.