Refresh performance optimizations for DRAM technologies with sub-channel and/or pseudo-channel configurations

A computing system comprising:

• a dual inline memory module (DIMM) having dynamic random access memory (DRAM) devices on a memory channel, the memory channel segmented into a first pseudo-channel and a second pseudo-channel by use of a double data rate command bus;
• and
• a controller coupled to the DRAM, wherein the controller includes logic and a first scheduling queue to queue memory access commands for the first pseudo-channel and a second scheduling queue to queue memory access commands for the second pseudo-channel;
• wherein when the first scheduling queue has a first refresh request for the first pseudo-channel and the second scheduling queue has a second refresh request for the second pseudo-channel, logic is to adjust a timing of one of the refresh requests to synchronize the first refresh request with the second refresh request to cause the first pseudo-channel and the second pseudo-channel to enter refresh concurrently.

A method comprising:

• queuing a first refresh request in a first scheduling queue for a first pseudo-channel of a dual inline memory module (DIMM) having dynamic random access memory (DRAM) devices on a memory channel, the memory channel segmented into the first pseudo-channel and a second pseudo-channel by use of a double data rate command bus;
• queuing a second refresh request a second scheduling queue for the second pseudo-channel;
• and
• adjusting a timing of one of the refresh requests to synchronize the first refresh request with the second refresh request to cause the first pseudo-channel and the second pseudo-channel to enter refresh concurrently.