Device and method for performing matrix operation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus Lu
Life of this patent
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Abstract
A system for processing a data array, such as transposing a matrix, includes a two-dimensional array of memory cells, such as FeFETs, each having an input end, an output end and a control end. The system also includes an input interface is adapted to supply signals indicative of a subset of the data array, such as a row of a matrix, and output control signals to the input ends of a selected column of the memory cells. The system further includes an output interface adapted to receive the data stored in the memory array from the output ends of a selected row of the memory cells. A method of processing a data array, such as transposing a matrix, include writing subsets of the data array to the memory array column-by-column, and reading from the memory cells, row-by-row.
Claims20
A system for implementing a matrix operation, the system comprising:
- a memory array having a plurality of memory cells arranged logically in rows and columns, each of the plurality of memory cells having an input end, an output end, and a control end;
- a plurality of input lines, each connected to the input ends of a respective row of the memory cells;
- a plurality of output lines, each connected to the output ends of a respective column of the memory cells;
- a plurality of select lines, each connected to the control ends of a respective row of the memory cells;
- and
- an input interface connected to the plurality of input lines and adapted to sequentially apply a plurality of sets of input signals, each set indicative of a respective column of values of elements of a matrix, to the input lines;
- an output interface connected to the plurality of output lines and adapted to sequentially receive from the output lines a plurality of sets of output signals, each set indicative of the elements stored in a respective row of the memory cells;
- and
- a selection signal interface connected to the plurality of select lines and adapted to supply selection signals to the select lines,
- wherein the output interface or selection signal interface, or both cooperatively, are adapted to select a column of the plurality of memory cells to enable the selected column of the plurality of memory cells to store a set of data corresponding to each respective one of the sets of input signals applied to the input lines, and
- wherein the input interface or selection signal interface, or both cooperatively, are adapted to select rows of the plurality of memory cells to enable the plurality of memory cells to output the elements stored in the plurality of memory cells to the output interface.
A system for processing an input data array having one or more one-dimensional data arrays, each having a set of multi-bit elements, the system comprising:
- a plurality of single-bit array processing systems, each comprising;
- a memory array having a plurality of memory cells arranged logically in rows and columns, each of the plurality of memory cells having an input end, an output end, and a control end;
- a plurality of input lines, each connected to the input ends of a respective row of the memory cells;
- a plurality of output lines, each connected to the output ends of a respective column of the memory cells;
- and
- a plurality of select lines, each connected to the control ends of a respective row of the memory cells;
- an input interface connected to the plurality of input lines of the plurality of single-bit array processing systems and adapted to sequentially apply a plurality of sets of input signals, each set indicative of a respective column of values of elements of a matrix, to supply a bit of each of the multi-bit elements of one of the one-dimensional data arrays to each of the respective input lines;
- an output interface connected to the plurality of output lines of each single-bit array processing system and adapted to receive from the output lines the elements stored in respective columns of the memory cells;
- and
- a selection signal interface connected to the plurality of select lines of each single-bit processing system and adapted to supply selection signals to the select lines;
- wherein the output interface and selection signal interface are adapted to select a column of the plurality of memory cells in each of the plurality of single-bit array processing systems to enable the column of the plurality of memory cells to store a set of data corresponding to each respective one of the sets of input signals applied to the input lines;
- wherein the input interface and selection signal interface are adapted to select rows of the plurality of memory cells in each of the plurality of single-bit array processing systems to enable, row-by-row, the plurality of memory cells to output the elements stored in of the plurality of memory cells to the output interface.
A method of implementing an array operation, the method comprising:
- sequentially applying a plurality of sets of input signals, each set indicative of a respective subset of digital values of elements of an array, to wordlines of a memory array having a plurality columns and rows of memory cells, each row of the memory cells being associated with a respective one of the wordlines;
- storing in the memory array a plurality of sets of data, each set in a respective one of the plurality of columns and corresponding to a respective one of the sets of input signals applied to the wordlines;
- and
- sequentially reading from the rows of the memory array the elements written to the memory cells.
Dependencies are inferred from the claim text.