Back to results
US 12,586,621 B2Granted
Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
OwnerKang-Yong Kiminventor
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
Claims24
An apparatus comprising:
- a controller configured to:
- provide a first mode register write command to a memory to write a first value for a duty cycle monitoring (DCM) start/stop opcode to cause the memory to perform a first DCM operation;
- and
- provide a second mode register write command to the memory to write a flip bit value for a DCM flip opcode to cause the memory to flip an input for a duty cycle monitor of the memory and perform a second DCM operation.
1 more element
A system comprising:
- a memory comprising:
- a mode register configured to store a plurality of opcodes;
- and
- a duty cycle monitor (DCM) configured to perform a DCM operation;
- and
- a controller coupled to the memory, the controller configured to:
- cause a first value or a second value to be written to a start/stop opcode of the plurality of opcodes, wherein the DCM operation is started responsive to the first value and the DCM operation is terminated responsive to the second value.
4 more elements
A method comprising:
- providing with a controller, a system clock signal to a plurality of memories;
- providing with the controller, a data clock signal to the plurality of memories;
- issuing from the controller to at least one memory of the plurality of memories, a first mode register write command to write a first value for a duty cycle monitoring (DCM) start/stop opcode in a mode register of the at least one memory;
- and
- performing with the at least one memory a first DCM operation.
2 more elements
Dependencies are inferred from the claim text.