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US 12,586,620 B2Granted
Memory device including sub-control circuit with asynchronous control logic
AssigneeYangtze Memory Technologies Co., Ltd.
InventorYue Sheng
Life of this patent
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Abstract
A memory device includes a memory array configured to store data, and a peripheral circuit coupled to the memory array and including a control logic circuit to control operations of the peripheral circuit. The control logic circuit includes a main control circuit and at least one first sub control circuit, and the main control circuit and the first sub control circuit interact through a first trigger signal and a first indication signal. The main control circuit and the first sub control circuit interact through an asynchronous control logic without a global clock signal.
Claims20
A memory device, comprising:
- a memory array configured to store data;
- and
- a peripheral circuit coupled to the memory array and comprising a control logic circuit to control operations of the peripheral circuit,
- wherein the control logic circuit comprises a main control circuit and at least one first sub control circuit, and the main control circuit and a first sub control circuit interact through a first trigger signal and a first indication signal,
- wherein the first sub control circuit comprises:
- an asynchronous control circuit configured to receive the first trigger signal from the main control circuit and generate a local clock signal, the asynchronous control circuit comprising:
- a first exclusive OR gate comprising a first input end, a second input end, and a first output end, wherein the first input end is configured to receive the first trigger signal, and the first output end is configured to output the local clock signal:
- a flip-flop circuit comprising an enable end coupled to the first output end of the first exclusive OR gate, a second output end, and a data end coupled to the second output end;
- and
- a first delay element disposed between the second input end of the first exclusive OR gate and the second output end of the flip-flop circuit and a state machine circuit configured to receive the local clock signal and generate the first indication signal.
7 more elements
A control logic circuit for control operations of a peripheral circuit of a memory device, comprising:
- a main control circuit and at least one sub control circuit interacting with each other through a first trigger signal and a first indication signal,
- where in a sub control circuit comprises:
- an asynchronous control circuit configured to receive the first trigger signal and generate a local clock signal, the asynchronous control circuit comprising:
- a first exclusive OR gate comprising a first input end, a second input end, and a first output end, wherein the first input end is configured to receive the first trigger signal, and the first output end is configured to output the local clock signal;
- a flip-flop circuit comprising an enable end coupled to the first output end of the first exclusive OR gate, a second output end, and a data end coupled to the second output end;
- and
- a first delay element disposed between the second input end of the first exclusive OR gate and the second output end of the flip-flop circuit;
- and
- a state machine circuit configured to receive the local clock signal and generate the first indication signal.
6 more elements
A method of operating a peripheral circuit of a memory device, comprising:
- generating a trigger signal by a main control circuit;
- receiving the trigger signal by a sub control circuit;
- generating a local clock signal in the sub control circuit;
- triggering a state machine circuit in the sub control circuit by the local clock signal;
- and
- generating an indication signal by the sub control circuit and transmitting the indication signal to the main control circuit,
- wherein the sub control circuit is configured to receive the trigger signal, by an asynchronous control circuit, from the main control circuit and generating, by the asynchronous control circuit, the local clock signal;
- and
- the asynchronous control circuit comprises an exclusive OR gate, a flip-flop circuit, and a delay element, and is configured to:
- receive the trigger signal, by a first input end of the exclusive OR gate, and output the local clock signal, by a first output end of the exclusive OR gate;
- and
- couple an enable end of the flip-flop circuit to the first output end of the exclusive OR gate, and couple a data end of the flip-flop circuit to a second output end of the flip-flop circuit.
9 more elements
Dependencies are inferred from the claim text.