Integrated circuit device and methods

An integrated circuit (IC) device, comprising:

• a substrate;
• and
• a memory array layer over the substrate, the memory array layer comprising a plurality of memory cells each comprising a set of memory elements, wherein
• the plurality of memory cells comprises a first memory cell, and a second memory cell adjacent the first memory cell along a first axis,
• the set of memory elements of the first memory cell and the set of memory elements of the second memory cell are electrically coupled to
• a same set of word lines,
• a same source line, and
• corresponding first and second bit lines, and
• the IC device further comprises, in the memory array layer and along the first axis, an isolation structure between the first memory cell and the second memory cell.

A method, comprising:

• patterning a multilayer structure comprising at least one memory array layer, to obtain
• an opening between a first portion and a second portion of the multilayer structure, and
• at least one channel extending across the opening from the first portion to the second portion, the at least one channel belonging to at least one active region layer in the at least one memory array layer;
• depositing a memory film around the at least one channel;
• depositing a conductive material in the opening;
• and
• patterning the deposited conductive material to obtain at least one gate electrode around at least one channel.