Memory system and memory die
AssigneeNanya Technology Corporation
InventorWu-Der Yang
Life of this patent
Estimating the term…
Abstract
Memory systems and memory dies are provided. The memory system of the present disclosure comprises a plurality of memory dies. The plurality of memory dies are stacked within the memory system. The plurality of memory dies respectively comprises a plurality of numbering circuits. The plurality of numbering circuits are coupled in series as a string. A current stage numbering circuit in the string comprises a plurality of sub-circuits. The plurality of sub-circuits are configured to respectively generate bits of a current stage number signal directly using bits of a previous stage number signal from a previous stage numbering circuit.
Claims20
A memory system, comprising:
- a plurality of memory dies stacked within the memory system, wherein each of the plurality of memory dies comprising:
- a numbering circuit, the numbering circuits in the memory dies being coupled in series as a string, wherein a current stage numbering circuit in the string comprises:
- a plurality of sub-circuits, each of the sub-circuits configured to generate a bit of a current stage number signal directly using only at least one bit of a previous stage number signal from a previous stage numbering circuit.
A memory die, adapted to be stacked within a memory system, the memory die comprising:
- a numbering circuit configured to generate a current stage number signal according to a previous stage number signal, the numbering circuit comprising:
- a plurality of sub-circuits, each of the sub-circuits configured to generate a bit of the current stage number signal directly using only at least one bit of the previous stage number signal.
Dependencies are inferred from the claim text.