Memory module and system supporting parallel and serial access modes
AssigneeRambus Inc.
InventorsScott C. Best, Frederick A. Ware, William N. Ng
Life of this patent
Estimating the term…
Abstract
A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
Claims20
A memory supporting a wide-data mode and a narrow-data mode, the memory comprising:
- memory devices;
- and
- at least one memory buffer having:
- a first data interface coupled to the memory devices;
- a first command interface coupled to the memory devices;
- a second data interface with a configurable data port supporting:
- a first data connection of a first data width to convey data in the wide-data mode;
- and
- a second data connection of a second data width, less than the first data width, in the narrow-data mode;
- and
- a second command interface with a configurable command port supporting:
- a first command connection of a first command width to convey memory commands in the wide-data mode;
- and
- a second command connection of a second command width, less than the first command width, to convey the memory commands in the narrow-data mode.
A memory comprising:
- a command buffer to facilitate communication between a memory controller and dynamic random-access memory (DRAM), the DRAM to store write data and provide read data, the command buffer including:
- a configurable command port to receive first memory-controller commands from the memory controller in a parallel-access mode, and to receive second memory-controller commands and the write data from the memory controller in a serial-access mode.
A memory comprising:
- a buffer system to facilitate communication between a memory controller and dynamic random-access memory (DRAM), the DRAM to store write data, the buffer system including:
- data buffers to communicate the write data from the memory controller to the DRAM in a parallel-access mode;
- and
- a configurable command port to receive first memory-controller commands from the memory controller in the parallel-access mode, and to receive second memory-controller commands and the write data from the memory controller in a serial-access mode.
Dependencies are inferred from the claim text.