An in-memory computation (IMC) device for performing a multiply-and-accumulate (MAC) operation, configured to receive an input signal indicative of a plurality of input values each having a respective sign and a respective absolute value, and to provide at least one output signal, the device comprising:
- a computation memory array comprising a plurality of groups of memory cells coupled to a bitline, each group of memory cells configured to store a respective computational weight and comprising a positive memory cell coupled to a respective positive wordline and a negative memory cell coupled to a respective negative wordline;
- and
- a row-activation circuit configured to receive the input signal and to provide, for each input value, during an effective elaboration interval, a positive-activation signal having a positive-activation duration to the positive wordline of a respective group of memory cells and a negative-activation signal having a negative-activation duration to the negative wordline of the respective group of memory cells, a sum of the positive-activation duration and the negative-activation duration being equal to a duration of the effective elaboration interval, the effective elaboration interval comprising a first elaboration phase and a second elaboration phase subsequent to the first elaboration phase;
- wherein the row-activation circuit is further configured, for each input value, to:
- determine a positive theoretical duration of the positive-activation signal and a negative theoretical duration of the negative-activation signal, wherein the positive theoretical duration and the negative theoretical duration are each an algebraic sum of a reference value that does not depend upon the input value and a variable value that varies as a function of the sign and the absolute value of the input value, so that the sum of the respective positive theoretical duration and the respective negative theoretical duration is equal to a theoretical elaboration duration;
- and
- provide first, during the effective elaboration interval, the positive-activation signal and the negative-activation signal whose theoretical durations are greater than or equal to the reference value, wherein the activation duration of one said positive-activation signal and the negative-activation signal being equal to the sum of an effective reference value, which is equal to the reference value reduced by a reduction factor, and the variable value, and wherein the activation duration of the other of said positive-activation signal and the negative-activation signal being equal to the respective theoretical duration;
- the first elaboration phase of the effective elaboration interval having a duration equal to the effective reference value;
- the positive memory cell of a respective group of memory cells being configured to be activated by the respective positive-activation signal and through which a positive-cell current flows when activated;
- the negative memory cell of the respective group of memory cells being configured to be activated by the respective negative-activation signal and through which a negative-cell current flows when activated;
- wherein, for each group of memory cells, the positive-cell current and the negative-cell current are a function of the respective computational weight stored by the group of memory cells;
- wherein a bitline current flows through the bitline during the effective elaboration interval that is a function of a sum of the positive-cell currents and the negative-cell currents of the groups of memory cells coupled to the bitline;
- a column-elaboration circuit coupled to the bitline and configured to sample the bitline current and provide, in response thereto, the at least one output signal, wherein the bitline current during the first elaboration phase is sampled as a function of the reduction factor.