Display having semiconducting oxide gate driver circuitry with bottom gate terminals for reduced leakage

A driver circuit configured to output a control signal to a row of display pixels, comprising:

• a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit, wherein the control signal is configured to be produced at the output port;
• a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line;
• a third transistor having a drain terminal coupled to the gate terminal of the second transistor, a gate terminal coupled to the gate terminal of the first transistor, a source terminal coupled to a second ground power supply line different than the first ground power supply line, and a bottom gate terminal shorted to its source terminal;
• a fourth transistor having a drain terminal coupled to the drain terminal of the third transistor, a source terminal coupled to the second ground power supply line, a gate terminal, and a bottom gate terminal shorted to its source terminal;
• and
• a first additional transistor having a gate terminal configured to receive a clock signal and a source-drain terminal coupled to the gate terminal of the fourth transistor.

A driver circuit configured to output a control signal to a row of display pixels, comprising:

• a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit, wherein the control signal is configured to be produced at the output port;
• a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line;
• a first discharge transistor having a drain terminal coupled to the output port of the driver circuit, a source terminal coupled to the first ground power supply line, a gate terminal configured to receive a clear signal, and a bottom gate terminal coupled to the first ground power supply line;
• a capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal;
• and
• a second discharge transistor having a drain terminal coupled to the second terminal of the capacitor, a source terminal coupled to a second ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the second ground power supply line.