Display driving circuit and display device

A display driving circuit, comprising two gate driving circuits, wherein the two gate driving circuits are respectively arranged on two opposite sides of a display panel;

• the gate driving circuit includes a plurality of cascaded driving circuits;
• the driving circuit includes N clock signal terminals, N output sub-circuits and N driving signal output terminals;
• N is an integer greater than or equal to 2;
• the N output sub-circuits share a first pull-up node;
• an nth output sub-circuit is used to control to output an nth driving signal through an nth driving signal output terminal according to an nth clock signal provided by an nth clock signal terminal under the control of a potential of the first pull-up node;
• n is a positive integer less than or equal to N;
• an ith driving signal output terminal of one of the two driving circuits is electrically connected to an (i+j)th driving signal output terminal of the other of the two driving circuits, and both i and j are positive integers, i is a positive integer less than or equal to N, j is a positive integer less than or equal to N, and i+j is a positive integer less than or equal to N;
• when a potential of an ith clock signal provided by the ith clock signal terminal among the N clock signal terminals jumps from an invalid level to a valid level, the potential of the first pull-up node is a first voltage value, when a potential of an (i+j)th clock signal provided by the (i+j)th clock signal terminal among the N clock signal terminals jumps from an invalid level to a valid level, the potential of the first pull-up node is a second voltage value;
• the first voltage value is not equal to the second voltage value;
• a time period during which the potential of the ith clock signal continues to be at the valid level and a time period during which the potential of the (i+j)th clock signal continues to be at the valid level at least partially overlap;
• a time point when the potential of the ith clock signal jumps from the valid level to the invalid level is different from a time point when the potential of the (i+j)th clock signal jumps from the valid level to the invalid level;
• wherein the driving circuit further includes a first input sub-circuit, a first pull-down sub-circuit, a first pull-down node control sub-circuit, and N output reset sub-circuits;
• the N output reset sub-circuits share the first pull-down node;
• the first input sub-circuit is configured to control the potential of the first pull-up node under the control of a first input signal provided by the first input terminal;
• the first pull-down sub-circuit is electrically connected to the first pull-up node, the first pull-down node, a first reset terminal and the first voltage terminal respectively, and is used to control to connect the first pull-up node and the first voltage terminal under the control of the potential of the first pull-down node, and control to connect the first pull-up node and the first voltage terminal under the control of a first reset signal provided by the first reset terminal;
• the first pull-down node control sub-circuit is electrically connected to a first control voltage terminal, the first pull-up node, the first pull-down node and the first voltage terminal, and is configured to control the potential of the first pull-down node under the control of a first control voltage provided by the first control voltage terminal and the potential of the first pull-up node, according to a first voltage signal provided by the first voltage terminal;
• an nth output reset sub-circuit is electrically connected to the first pull-down node, a second voltage terminal, and an nth driving signal output terminal, and is used to control to connect the nth driving signal output terminal and the second voltage terminal under the control of the potential of the first pull-down node.