Fast controller device for controlling a quantum processor

A controller device for controlling a quantum processor comprising:

• a plurality of input channels,
• a plurality of output channels,
• an input interface connected to said input channels,
• a register bank comprising a plurality of registers connected to said input interface,
• a feedback block having inputs connected to said register bank and outputs,
• an output interface connecting the outputs of the feedback block to the output channels,
• wherein said input interface comprises a plurality of address decoders, with different address decoders being attributed to different input channels,
• wherein each address decoder is part of an update decoder, with different update decoders being attributed to different input channels,
• wherein said update decoder is adapted and structured to decode update messages from its input channel, with each update message comprising:
• address data indicative of at least one register in the register bank,
• at least one data value indicative of a value to be stored in the register indicated by the address data,
• at least one validity bit indicative of a validity of said data value.