Hardware architecture for introducing activation sparsity in neural network
AssigneeNumenta, Inc.
InventorsKevin Lee Hunter, Subutai Ahmad
Life of this patent
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AssigneeNumenta, Inc.
InventorsKevin Lee Hunter, Subutai Ahmad
Estimating the term…
A hardware accelerator that is efficient at performing computations related to a sparse neural network. The sparse neural network may be associated with a plurality of nodes. An artificial intelligence (AI) accelerator stores, at a memory circuit, a weight tenor and an input activation tensor that corresponds to a node of the neural network. The AI accelerator performs a computation such as convolution between the weight tenor and the input activation tensor to generate an output activation tensor. The AI accelerator introduces sparsity to the output activation tensor by reducing the number of active values in the output activation tensor. The sparsity activation may be a K-winner approach, which selects the K-largest values in the output activation tensor and set the remaining values to zero.
An artificial intelligence accelerator for performing operations related to a neural network, comprising:
A computer-implemented method for processing a neural network, the computer-implemented method comprising:
A computing device, comprising:
Dependencies are inferred from the claim text.