Sysnapse circuit for preventing errors in charge calculation and spike neural network circuit including the same
AssigneeElectronics and Telecommunications Research Institute
InventorsKwang Il Oh, Tae Wook Kang, Hyuk Kim, Jae-Jin Lee
Life of this patent
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Abstract
Disclosed is a synaptic circuit including a weight memory that stores a weight value, a current-mode digital-to-analog converter (C-DAC) circuit that receives the weight value from the weight memory and supplies a current based on the weight value, a parasitic capacitor correction circuit that receives the weight value from the weight memory and to correct a value of parasitic capacitance generated by the C-DAC circuit based on the weight value, and a pre-discharge circuit that drains charges accumulated by the parasitic capacitance.
Claims13
A synaptic circuit comprising:
- a weight memory configured to store a weight value;
- a current-mode digital-to-analog converter (C-DAC) circuit configured to receive the weight value from the weight memory and to supply a current based on the weight value;
- a parasitic capacitor correction circuit configured to receive the weight value from the weight memory and to correct a value of parasitic capacitance generated by the C-DAC circuit based on the weight value;
- and
- a pre-discharge circuit configured to drain charges accumulated by the parasitic capacitance.
A spike neural network (SNN) circuit comprising:
- a synaptic circuit array including a plurality of synaptic circuits arranged in ‘n’ rows and ‘m’ columns;
- a plurality of spike generators electrically connected to correspond to the ‘n’ rows, respectively;
- a plurality of neuron circuits electrically connected to correspond to the ‘m’ columns, respectively;
- and
- a plurality of membrane capacitors electrically connected to correspond to the ‘m’ columns, respectively,
- wherein each of the plurality of synaptic circuits includes:
- a weight memory configured to store a weight value;
- a C-DAC circuit configured to receive the weight value from the weight memory and to supply a current based on the weight value;
- a parasitic capacitor correction circuit configured to receive the weight value from the weight memory and to correct a value of parasitic capacitance generated by the C-DAC circuit based on the weight value;
- and
- a pre-discharge circuit configured to drain charges accumulated by the parasitic capacitance.
Dependencies are inferred from the claim text.