Graph-based approach towards hardware trojan vulnerability analysis

A system comprising:

• a processor;
• and
• a memory having instructions that, when executed by the processor, cause the processor to:
• detect a hardware trojan triggering signal in a design of an integrated circuit, using a graph-based analysis that is golden-design agnostic comprising:
• performing a simulation of an application of a test pattern running on an integrated circuit having the design, which simulates gate-level activity of the integrated circuit;
• capturing switching activity of nodes for the design of the integrated circuit during the simulation;
• identifying one or more nodes in a graphical representation of the design that do not toggle within an individual window of time of a sequence of multiple, non-overlapping windows of time during the simulation, wherein each window of time has a same period comprising a predetermined time period of two or more consecutive clock cycles;
• identifying a set of rare paths of the design for each window of the sequence of multiple, non-overlapping windows of time, wherein each rare path for a given window:
• is comprised of two or more nodes identified as not having toggled within the given window;
• has distinct endpoints which are not in the same graph level;
• and
• is not a segment of a critical path of the design;
• determining a subset of unique rare paths of the set of rare paths for each window of the sequence of multiple non-overlapping windows of time, wherein each unique rare path is not a segment of another rare path within a same window;
• identifying one or more unique rare paths of the design that occur across consecutive windows of time;
• appending the one or more unique rare paths that occur across the consecutive windows of time in a set of dominating unique rare paths;
• and
• output the one or more unique rare paths in the set of dominating unique rare paths as rare trojan horse triggering paths for the design.

A method comprising:

• detecting, by a computing device, a hardware trojan triggering signal in a design of an integrated circuit, using a graph-based analysis that is golden-design agnostic comprising:
• performing a simulation of an application of a test pattern running on an integrated circuit having the design, which simulates gate-level activity of the integrated circuit;
• capturing switching activity of nodes for the design of the integrated circuit during the simulation;
• identifying one or more nodes in a graphical representation of the design that do not toggle within an individual window of time of a sequence of multiple, non-overlapping windows of time during the simulation, wherein each window of time has a same period comprising a predetermined time period of two or more consecutive clock cycles;
• identifying a set of rare paths of the design for each window of the sequence of multiple, non-overlapping windows of time, wherein each rare path for a given window:
• is comprised of two or more nodes identified as not having toggled within the given window;
• has distinct endpoints which are not in the same graph level;
• and
• is not a segment of a critical path of the design;
• determining a subset of unique rare paths of the set of rare paths for each window of the sequence of multiple non-overlapping windows of time, wherein each unique rare path is not a segment of another rare path within a same window;
• identifying one or more unique rare paths of the design that occur across consecutive windows of time;
• appending the one or more unique rare paths that occur across the consecutive windows of time in a set of dominating unique rare paths;
• and
• outputting the one or more unique rare paths in the set of dominating unique rare paths as rare trojan horse triggering paths for the design.