US 12,585,780 B2 · Secure stacking of memory dies

Abstract

An IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary Chip Select (CS) signal via a primary CS line that connects to the primary memory die. The secondary memory die is coupled to the bus, excluding the primary CS line, and to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command over the bus, while the primary CS signal is active, in response to identifying that the command is destined to the primary memory die, to execute the command within the primary memory die, and in response to identifying that the command is destined to the secondary memory die, to cause the secondary memory die to execute the command by transferring the primary CS signal on the secondary CS line.

Claims24

Dependent claims

An Integrated Circuit (IC), comprising:

a primary memory die, which is connected to a bus comprising multiple signals including a Chip Select (CS) signal;
and
a secondary memory die, which is connected to the multiple signals of the bus except for the CS signal,
wherein the primary memory die comprises (i) a local memory, and (ii) CS logic, the CS logic configured to:
receive a command over the bus while the CS signal is active;
in response to identifying that the command is destined to the primary memory die, connect the CS signal to the local memory and not to the secondary memory die, thereby causing the primary memory die to execute the command;
and
in response to identifying that the command is destined to the secondary memory die, connect the CS signal to the secondary memory die and not to the local memory, thereby causing the secondary memory die to execute the command.

5 more elements

Dependencies are inferred from the claim text.

Secure stacking of memory dies

Life of this patent

Secure stacking of memory dies

Life of this patent

Abstract

Claims24