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US 12,585,608 B2Granted
Architecture to achieve higher throughput in symbol to wire state conversion
AssigneeXilinx, Inc.
InventorsKondala Rao Polisetti, Anil Kumar Chimbeti, Narendra Gochika, Narasimha Rao Marisetty
Life of this patent
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Abstract
Embodiments herein describe techniques for converting multiple symbols into respective wire states in parallel. In one embodiment, the techniques can be used to convert symbols into wire states in parallel even when those wire states are dependent on previously determined wire states. That is, the dependency on previous wire states can be removed so that wire states can be determined in parallel.
Claims20
A transmitter, comprising:
- a symbol mapper comprising circuitry configured to map data into a plurality of symbols having a defined order;
- a symbol encoder configured to receive the plurality of symbols from the symbol mapper in parallel, the symbol encoder comprising circuitry configured to convert the plurality of symbols into respective wire states concurrently using parallel logic circuitry and without relying on prior symbol transitions, and to output the wire states in parallel in a same clock cycle;
- and
- an interface configured to transmit the wire states to a receiver using a link.
1 more element
A method, comprising:
- converting data into a plurality of symbols;
- providing the plurality of symbols to a symbol encoder in parallel;
- encoding, by the symbol encoder, the plurality of symbols into respective wire states concurrently using parallel logic circuitry and without relying on transitions between symbols, and outputting the wire states in parallel in a same clock cycle;
- and
- transmitting, via a transmitter, the wire states to a receiver using a link.
2 more elements
A transmitter comprising:
- a symbol mapper comprising circuitry configured to map data into a plurality of symbols having a defined order;
- a symbol encoder configured to receive the plurality of symbols from the symbol mapper in parallel, the symbol encoder comprising circuitry configured to convert the plurality of symbols into respective wire states concurrently using parallel logic circuitry and without relying on transitions between symbols and to output the wire states in parallel in a same clock cycle to lower clock speeds of the transmitter;
- and
- an interface configured to transmit the wire states to a receiver using a link.
1 more element
Dependencies are inferred from the claim text.