Coarse grained reconfigurable architecture

An integrated circuit (IC), comprising:

• a plurality of packet processing engines (PPEs) each comprising a plurality of stages, wherein each of the plurality of stages comprises arithmetic logic units (ALUs) that are reconfigurable to perform different functions when processing different packets;
• and
• a packet bus interconnecting the plurality of PPEs, wherein the plurality of PPEs are sequenced to form a chain, wherein the packet bus is configured to pass a packet to be processed by each of the plurality of PPEs along the chain,
• wherein a first PPE of the plurality of PPEs is configured to, during a first clock cycle, process the packet according to a first processing program of a plurality of packet processing programs, and to provide, based on the processing, control signals separate from the processed packet to a plurality of context memories corresponding to different downstream PPEs of the plurality of PPEs,
• wherein the control signals:
• indicate, to a second PPE of the downstream PPEs, a second packet processing program, of the plurality of packet processing programs, to use to further process the processed packet, and
• configure the ALUs of at least the second PPE to perform functions of the second processing program on the processed packet during a second clock cycle, and
• wherein the first processing program and the second processing program are different programs performing respective functions.

A method, comprising:

• determining, using a first packet processing engine (PPE) in an integrated circuit (IC), to process a first packet using a first program and to process a second packet using a second program, wherein the first program and the second program are different programs performing respective functions;
• providing, from the first PPE, first control signals separate from the first packet to a plurality of context memories corresponding to different downstream PPEs in the IC, wherein the first control signals indicate the first program from a plurality of packet processing programs;
• configuring, using outputs of the context memory corresponding to a second PPE, a first stage in the second PPE to perform a first step in the first program to process the first packet in a first clock cycle;
• providing second control signals separate from the second packet to the plurality of context memories that indicate the second program from the plurality of packet processing programs;
• and
• reconfiguring, using the outputs of the context memory corresponding to the second PPE, the first stage in the second PPE to perform a first step in the second program to process the second packet in a second clock cycle,
• wherein the first and second PPEs are part of a chain of PPEs interconnected by a packet bus, wherein the first and second packets are processed by every PPE in the chain of PPEs.