US 12,585,604 B2Granted

Efficient chip-to-chip communications

AssigneeNVIDIA Corporation

InventorsAnurag Chaudhary, Guan Wang, Harsh Kumar

Life of this patent

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Abstract

In various examples, when a bridge of a chip has received an eviction request from a client of the chip, the bridge may transmit a read request that corresponds to the same cache line to another chip without waiting for an inter-chip completion response for the eviction request. When the read request is received, the bridge may determine whether the eviction request has already been sent to the other chip and transmit the read request based at least on the eviction request being sent to the other chip using an ordered communication network to ensure the communications are received and/or processed by the other chip in an order that maintains memory coherency. Additionally, the chips may process read unique requests without using an inter-chip completion acknowledgement and may process copy back requests by transmitting corresponding copy back write data with the copy back requests.

Claims20

Dependent claims

A method comprising:

receiving, by an interconnect bridge of a first chip, an eviction request from a client of the first chip;
determining, by the interconnect bridge of the first chip, a message of a different transaction than the eviction request;
based at least on the message corresponding to a same cache line as the eviction request and the eviction request being of an eviction request type, determining, by the interconnect bridge, whether the eviction request has been transmitted to a second chip using an ordered communication fabric between the first chip and the second chip, the ordered communication fabric and the second chip configured to guarantee that the eviction request and the message are completed by the second chip in an order in which the interconnect bridge transmits the eviction request and the message over the ordered communication fabric;
and
based at least on the determining whether the eviction request has been transmitted and the eviction request being transmitted to the second chip using the ordered communication fabric, transmitting, by the interconnect bridge and without the first chip waiting for the second chip to complete the eviction request, the message to the second chip using the ordered communication fabric.

2 more elements

At least one processor comprising:

one or more circuits of a first chip to:
receive a request to relinquish, from a client, ownership permissions of a portion of memory with respect to at least two clients;
receive a message corresponding to the portion of memory;
determine the message and the request to relinquish ownership permissions correspond to the portion of memory;
and
based at least on the message and the request corresponding to the portion of memory and the request being of an eviction request type, push, over an ordered communication fabric and without the first chip waiting for a second chip to complete the request, the request to relinquish ownership of the portion of memory to the second chip using the message, the ordered communication fabric and the second chip configured to guarantee that the request and the message are completed by the second chip in an order in which the first chip transmits the request and the message over the ordered communication fabric.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/449,979Filed 15 Aug 2023
Published: US 2025/0061078 A120 Feb 2025
Granted: 24 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 13/4031
Using bus bridges: with arbitration
G06F 12/0831
Cache consistency protocols: using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0835
Using a bus scheme, e.g. with bus monitoring or watching means: for main memory peripheral accesses
G06F 13/4027
Coupling between buses: using bus bridges