Systems and methods for processor circuits

A processor circuit comprising:

• a first front-end circuit for scheduling first and second threads for a first application program;
• a first processing circuit that processes first operations in the first thread;
• a second processing circuit that processes second operations in the second thread;
• a thread scheduler circuit that causes the first front-end circuit to schedule processing of the first operations on the first processing circuit, wherein the thread scheduler circuit causes the first front-end circuit to schedule processing of the second operations on the second processing circuit, and wherein the thread scheduler circuit causes the first processing circuit to process one of the first operations concurrently with the second processing circuit processing one of the second operations;
• and
• a first register file that stores first architectural states for a matrix shared by the first and the second threads.

A method for processing first and second application programs using a processor circuit, the method comprising:

• scheduling first instructions for the first application program using a first front-end circuit;
• scheduling second instructions for the second application program using a second front-end circuit;
• causing the first front-end circuit to schedule processing of first operations in the first instructions on a back-end processing circuit using a multi-program scheduler circuit;
• causing the second front-end circuit to schedule processing of second operations in the second instructions on the back-end processing circuit using the multi-program scheduler circuit;
• processing the first operations and the second operations using the back-end processing circuit;
• storing a first architectural state in a first register file for a first private vector shared by a first subset of the first operations in a first thread in the first application program;
• storing a second architectural state in a second register file for a second private vector shared by a second subset of the first operations in a second thread in the first application program;
• and
• managing sharing between the first and the second architectural states using a front-end scheduler circuit to prevent collisions between data accesses to the first and the second register files.