Unified instruction processor for direct memory access scatter/gather engine

A network interface card (NIC) comprising circuitry to:

• receive, by a processing resource of the NIC, inputs including an instruction to read or write a payload of a message, a tracker state indicating a round of processing for the instruction, and a descriptor of a datatype defining organization of the message payload;
• identify a current context and a processing state for the instruction;
• in response to the datatype descriptor indicating a first type:
• obtain the current context associated with the first type from a host memory or a cache of the NIC;
• set the processing state to a first execution state;
• and
• create direct memory access (DMA) instructions corresponding to the received instruction by executing operations in a nested loop which represents a multi-dimensional array structure of the first type;
• and
• in response to the datatype descriptor indicating a second type:
• obtain the current context associated with the second type by fetching vector entries from a buffer of the NIC;
• set the processing state to a second execution state;
• and
• create the DMA instructions corresponding to the received instruction based on addresses and lengths in the vector entries of the second type.

A non-transitory computer-readable medium storing instructions to:

• receive inputs including an instruction to read or write a payload of a message, a tracker state indicating a round of processing for the instruction, and a descriptor of a datatype defining organization of the message payload;
• identify a current context and a processing state for the instruction;
• in response to the datatype descriptor indicating a first type:
• obtain the current context associated with the first type from a host memory or a cache;
• set the processing state to a first execution state;
• and
• create direct memory access (DMA) instructions corresponding to the received instruction by executing operations in a nested loop which represents a multi-dimensional array structure of the first type;
• and
• in response to the datatype descriptor indicating a second type:
• obtain the current context associated with the second type by fetching vector entries from a buffer;
• set the processing state to a second execution state;
• and
• create the DMA instructions corresponding to the received instruction based on addresses and lengths in the vector entries of the second type.