Memory with write address delay circuit
AssigneeSanDisk Technologies LLC
InventorsLunkai Zhang, Rasmus Madsen, Martin Lueker-Boden
Life of this patent
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Abstract
An apparatus includes control circuits configured to connect to a memory structure. The control circuits are configured to receive a write request that includes a logical address with write data corresponding to the logical address, encrypt the write data to obtain encrypted write data and map the logical address to a physical address in the memory structure. The control circuits are further configured to delay output of the physical address by a delay period to align output of the physical address and the encrypted write data.
Claims20
An apparatus, comprising:
- one or more control circuits configured to connect to a memory structure, the one or more control circuits configured to:
- receive a write request that includes a logical address with write data corresponding to the logical address, encrypt the write data to obtain encrypted write data and map the logical address to a physical address in the memory structure, delay output of the physical address by a delay period to align output of the physical address and the encrypted write data.
A method comprising:
- receiving a write request with a logical address and write data corresponding to the logical address;
- encrypting the write data to generate encrypted write data;
- while encrypting the write data, mapping the logical address to a physical address in a nonvolatile memory structure;
- applying a delay period to cause the physical address to be sent in parallel with the encrypted write data or later than the encrypted write data;
- and
- subsequently, writing the encrypted write data at the physical address in the nonvolatile memory structure.
A system comprising:
- a nonvolatile memory structure;
- and
- means for receiving a write request with a logical address and write data corresponding to the logical address, encrypting the write data to generate encrypted write data, mapping the logical address to a physical address in the nonvolatile memory structure while encrypting the write data and applying a delay period to cause the physical address to be sent in parallel with the encrypted write data or later than the encrypted write data.
Dependencies are inferred from the claim text.