Processor cross-core cache line contention management

A system comprising:

• a plurality of processors each comprising two or more cores forming a symmetric multiprocessing system;
• a cache system;
• and
• a controller coupled to the cache system, the controller configured to:
• send a cross-invalidate command to one or more caches of the cache system based on receiving a cache state change request for a cache line;
• determine a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches;
• wait until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches;
• and
• grant the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.

A computer-implemented method comprising:

• sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system;
• determining a ticket identifier based on receiving a cross-invalidate reject response with a ticket code from at least one of the one or more caches;
• waiting until a wakeup message associated with the ticket identifier has been received to resend the cross-invalidate command to the one or more caches;
• and
• granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.