Memory module having volatile and non-volatile memory subsystems and method of operation

A method at a memory module comprising dynamic random access memory (DRAM), Flash memory, and a module controller coupled to the DRAM and the Flash memory, comprising:

• receiving first data to be transferred from the DRAM to the Flash memory;
• computing first cyclic redundancy check (CRC) codes from the first data;
• writing the first data into first locations in the Flash memory;
• receiving second data by reading the first data from the first locations in the Flash memory;
• storing a copy of the second data in local memory;
• transferring the second data to the DRAM after receiving the second data from the Flash memory;
• computing second CRC codes from the copy of the second data stored in the local memory;
• comparing the second CRC codes with the first CRC codes to determine whether the copy of the second data includes one or more erroneous data bits;
• in response to determining one or more erroneous data bits in one or more segments of the copy of the second data, reading from the DRAM one or more segments of the second data, the one or more segments of the second data corresponding to the one or more segments of the copy of the second data and including one or more erroneous data bits corresponding to the one or more erroneous data bits in the copy of the second data;
• correcting the one or more erroneous data bits in the one or more data segments of the second data to obtain one or more corrected data segments;
• and
• writing the one or more corrected data segments back into the DRAM.

A device operable to control data transfers to and/or from first memory, comprising:

• a first interface configured to interface with the first memory;
• and
• control logic coupled to the first interface and configurable to:
• compute first cyclic redundancy check (CRC) codes for data to be transferred to the first memory, the data to be transferred to the first memory including first data bits;
• write the data to be transferred to the first memory into the first memory via the first interface;
• receive data read from the first memory via the first interface, the data read from the first memory including second data bits corresponding, respectively, to the first data bits;
• compute second CRC codes for the data read from the first memory;
• and
• compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the first memory;
• wherein the control logic is configurable to:
• arrange the first data bits into first data sets, and performing error correction coding on each respective data set of the first data sets to obtain a respective CRC code for the respective data set, each data set of the first data sets including a plurality of data bits from the first data bits, wherein each data bit of the first data bits is assigned to at least two intersecting data sets of the first data sets, and no two datasets of the first data sets have more than one data bit in common;
• arrange the second data bits into second data sets, and performing error correction coding on each individual data set of the second data sets to obtain individual CRC code for the individual data set, wherein the second data sets correspond, respectively, to the first data sets, and data bits in each data set of the second data sets correspond, respectively, to data bits in a corresponding data set of the first data sets;
• in response to the CRC codes of one or more data sets in the second data sets not matching the CRC codes of one or more corresponding data sets in the first data sets, determine one or more intersecting data sets of the second data sets, each intersection data set of the one or more intersecting data sets having a CRC code not matching the CRC code of a corresponding data set of the first data sets and having one data bit in common with one of the one or more data sets in the second data sets;
• and
• determine one or more erroneous data bits in the second data bits based on the one or more data sets in the second data sets and the one or more intersecting data sets of the second data sets.