Memory system
AssigneeSTMicroelectronics International N.V.
InventorRaphael Clauss
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.
Claims22
A memory system, comprising:
- a memory comprising memory blocks;
- a first logic circuit configured to perform an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet comprising one of:
- an error correction code of a data element to be written;
- said data element to be written;
- or a combination of an error correction code of a data element to be written and said data element to be written;
- wherein a second data packet output by the first logic circuit is stored in one of the memory blocks;
- and
- a second logic circuit configured to perform an XOR combinational logic function of at least one bit of the second data packet read from said one of the memory blocks and of the current value of the addressing mode during the reading of the second packet or subsequently thereto;
- wherein a weight of said at least one bit of the first data packet corresponds to a weight of said at least one bit of the second read data packet.
A method of securing a memory system that includes a memory comprising memory blocks, the method comprising:
- first logically combining with an XOR combinational logic function a current value of a data addressing mode and at least one bit of a first data packet comprising one of:
- an error correction code of a data element to be written;
- said data element to be written;
- or a combination of said error correction code of a data element to be written and said data element to be written;
- storing a second data packet generated by said first logically combining into one of the memory blocks;
- second logically combining with an XOR combinational logic function at least one bit of the second packet such as read from said one of the memory blocks, and the current value of the addressing mode during the reading of the second packet or subsequently thereto;
- wherein a weight of said at least one bit of the first data packet corresponds to a weight of said at least one bit of the second read data packet.
Dependencies are inferred from the claim text.