Trace cache access prediction and read enable

A method, comprising:

• predicting, by a computing system, directions of control transfer instructions executed by a processor of the computing system;
• caching, by the computing system in instruction cache circuitry, instructions sequentially in a given cache line;
• identifying, by the computing system, traces of instructions that satisfy one or more criteria, wherein one or more of the identified traces include at least one internal taken control transfer instruction;
• storing, by the computing system in a trace cache, identified traces;
• predicting, by the computing system, whether a fetch address will hit in the trace cache;
• and
• in response to a prediction that the fetch address will not hit in the trace cache;
• accessing tag circuitry for the trace cache based on the fetch address;
• reading instruction data from the instruction cache circuitry for the fetch address;
• and
• preventing instruction data being read from not the trace cache for the fetch address regardless of whether there is a tag match in the tag circuitry.

A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:

• processor circuitry configured to execute control transfer instructions;
• prediction circuitry configured to predict directions of control transfer instructions;
• instruction cache circuitry configured to cache instructions sequentially in a given cache line;
• trace cache circuitry configured to:
• identify traces of instructions that satisfy one or more criteria, wherein one or more of the identified traces include at least one internal taken control transfer instruction;
• and
• store identified traces, wherein the processor circuitry is configured to determine whether to access instructions from the instruction cache circuitry or the trace cache circuitry when there is a hit in both the trace cache circuitry and the instruction cache circuitry;
• read prediction circuitry configured to predict whether a fetch address will hit in the trace cache circuitry;
• and
• front-end circuitry configured to, in response to a prediction that the fetch address will not hit in the trace cache circuitry:
• access tag circuitry for the trace cache circuitry based on the fetch address;
• read instruction data from the instruction cache circuitry for the fetch address;
• and
• prevent instruction data being read from not the trace cache circuitry for the fetch address regardless of whether there is a tag match in the tag circuitry.