Apparatus and method using hint capability for controlling micro-architectural control function

An apparatus comprising:

• processing circuitry configured to perform data processing in response to instructions;
• capability storage circuitry configured to store at least one capability, each capability specifying a capability value and capability metadata indicative of constraints on valid use of the capability value;
• capability checking circuitry configured to determine whether a capability-controlled operation to be performed by the processing circuitry with reference to a target capability is allowed, based on whether the capability-controlled operation satisfies the constraints indicated by the capability metadata of the target capability, and to trigger an error handling response when the capability-controlled operation fails to satisfy the constraints indicated by the capability metadata of the target capability;
• and
• micro-architectural control circuitry configured to control a micro-architectural control function, other than determining whether the capability-controlled operation is allowed, depending on the capability metadata specified by a hint capability used to provide a hint to the micro-architectural control function,
• in which the micro-architectural control circuitry comprises vector load/store control circuitry configured to issue, in response to a vector load/store instruction, a load/store request to transfer data between memory and a first active vector element of a vector register and to issue one or more speculative load/store requests to transfer data between memory and one or more remaining active vector elements of the vector register before it is known how many of the vector elements actually require data to be transferred, and the vector load/store control circuitry is configured to suppress issuing of a speculative load/store request for a remaining active vector element corresponding to an address outside permitted bounds indicated by bounds information specified by the capability metadata of the target capability used as an address operand for the vector load/store instruction.

An apparatus comprising:

• processing circuitry configured to perform data processing in response to instructions;
• capability storage circuitry configured to store at least one capability, each capability specifying a capability value and capability metadata indicative of constraints on valid use of the capability value;
• capability checking circuitry configured to determine whether a capability-controlled operation to be performed by the processing circuitry with reference to a target capability is allowed, based on whether the capability-controlled operation satisfies the constraints indicated by the capability metadata of the target capability, and to trigger an error handling response when the capability-controlled operation fails to satisfy the constraints indicated by the capability metadata of the target capability;
• and
• micro-architectural control circuitry configured to control a micro-architectural control function, other than determining whether the capability-controlled operation is allowed, depending on the capability metadata specified by a hint capability used to provide a hint to the micro-architectural control function,
• in which the micro-architectural control circuitry comprises cache control circuitry configured to control allocation or replacement of entries in at least one cache, and in which at least one of:
• the capability metadata of a given capability specifies bounds information specifying permitted bounds for the capability value or a value derived from the capability value and permissions information specifying permitted types of capability-controlled operations permitted to be performed with reference to the given capability, and the cache control circuitry is configured to select, based on the permissions information of the hint capability, a coherency state to be used for allocation of a given cache entry associated with an address in an associated address range indicated by the bounds information of the hint capability;
• the cache control circuitry is configured to control, depending on the capability metadata specified by the hint capability, selection of a victim entry to be replaced in the at least one cache;
• and/or
• the cache control circuitry is configured to select, depending on reuse hint information specified by the capability metadata of the hint capability, at least one of:
• whether a cache entry should be allocated at all for data or instructions associated with addresses in a range indicated by bounds information specified by the capability metadata of the hint capability, and/or which of a plurality of cache levels of a cache hierarchy is a target cache level to be allocated with data or instructions for addresses in a range indicated by bounds information specified by the capability metadata of the hint capability.