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US 12,585,467 B2Granted
High level graph computing system
OwnerJoshua Huang, Hsilin Huanginventors
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Abstract
A Data Flow processor (DFP or DFPU) including a plurality of loop registers to effectively control the processing of multi-dimensional data; and a plurality of stride registers that are operable for precise addressing of data, enabling comprehensive management of data fetching, execution, accumulation, and result write-back processes; and wherein the processor is configured to be operable for high-dimensional computing.
Claims30
A processor comprising:
- at least one or more work group(s) of feature map(s);
- at least one Or more work group(s) of weight(s);
- at least one or more loop register(s), said one or more loop register(s) is/are configured to be operable for controlling the processing of multi-dimensional data;
- wherein said at least one or more loop register(s) is/are configured to ore and/or manage at least one of said one or more work group(s) of feature map(s), one or more work group(s) of weight(s), and to accumulate at least one or more value(s) in one or more accumulator(s);
- at least one or more stride register(s), said one or more stride register(s) is/are configured to be operable for at least one of, addressing of data, enabling comprehensive management of data fetching, execution, accumulation, and result write-back processes;
- wherein said one or more stride register(s) is/are configured to store and/or manage at least one of said, one or more work group(s) of feature map(s), one or more work group(s) of weight(s), and to accumulate at least one or more value(s) in said one or more accumulator(s);
- wherein said processor comprises at least one or more Data Flow Processor (DFP or DFPU) that is/are configured to be operable for high-dimensional computing,
- streamlining data retrieval, synchronization, execution, and/or storage processes;
- and
- wherein said one or more stride register(s) is/are further configured to enhance the processor's capacity for said high-dimensional computing, streamlining data retrieval, synchronization, execution, and/or storage processes.
7 more elements
A processor comprising:
- a plurality of loop registers to effectively control the processing of multi-dimensional data;
- at least one or more feature stride registers, wherein said at least one or more feature stride registers is/are configured to specify locations of features in multiple dimensions, across multiple cores, chips, or systems;
- at least one or more weight stride registers, wherein said at least one or more weight stride registers is/are configured to define locations within multiple addresses in a core, across different cores, chips, or systems;
- at least one or more a result stride registers, wherein said at least one or more a result stride registers is/are configured to specify result addresses across multiple dimensions;
- and
- wherein said processor comprises a Data Flow Processor (DFP or DFPU) that is configured to be operable for high-dimensional computing.
3 more elements
A processor comprising:
- a fLoop registers set, wherein said fLoop registers set is configured to define address strides for each count and dimension;
- a wLoop registers set, wherein said wLoop registers set is configured to serve as weight loop count registers for multiple dimensions;
- an arithmetic logic unit (ALU), wherein said ALU comprises a multi-dimensional adder tree group;
- an aLoop registers set, wherein said aLoop registers set is configured to control said ALU actions, including action type, action direction, and/or result write-back;
- at least one or more stride register(s) that is/are operable for addressing of data, enabling comprehensive management of data fetching, execution, accumulation, and result write-back processes;
- and
- wherein said processor comprises a Data Flow Processor (DFP or DFPU) that is configured to be operable for high-dimensional computing.
4 more elements
Dependencies are inferred from the claim text.