In-memory computing processor, processing system, processing apparatus, deployment method of algorithm model

An in-memory computing processing system, comprising a third master control unit and a plurality of in-memory computing processors,

• each of the plurality of in-memory computing processors comprises a first master control unit and a plurality of memristor processing modules,
• wherein the first master control unit is configured to be capable of dispatching and controlling the plurality of memristor processing modules,
• the plurality of memristor processing modules are configured to be capable of calculating under the dispatch and control of the first master control unit, and
• the plurality of memristor processing modules are further configured to be capable of communicating independently of the first master control unit to calculate to implement a computing task together;
• wherein the third master control unit is configured to be capable of dispatching and controlling the plurality of in-memory computing processors;
• the plurality of in-memory computing processors are configured to be capable of calculating under the dispatch and control of the third master control unit;
• the plurality of in-memory computing processors are further configured to be capable of communicating independently of the third master control unit, and
• wherein each of the plurality of memristor processing modules comprises a plurality of memristor processing units, each of the plurality of memristor processing units comprises a memristor array, and the memristor array comprises a plurality of rows and columns of memristors arranged in an array;
• wherein each in-memory computing processor further comprises:
• a routing module and an input-output module,
• the routing module is configured to receive input data, parse the input data to obtain an input signal, and transmit the input signal to the input-output module,
• wherein the in-memory computing processor is configured to support a first computing mode, and in the first computing mode:
• the input-output module is configured to distribute and transmit the input signal to at least one memristor processing module of the plurality of memristor processing modules,
• the at least one memristor processing module is configured to calculate according to the input signal to obtain a first output signal,
• the input-output module is further configured to receive and collate the first output signal from the at least one memristor processing module to obtain first output data, and
• the routing module is further configured to output the first output data.

An in-memory computing processing apparatus, comprising:

• an in-memory computing processor, an input interface and an output interface connected to the in-memory computing processor,
• wherein the in-memory computing processor comprises a first master control unit and a plurality of memristor processing modules,
• wherein the first master control unit is configured to be capable of dispatching and controlling the plurality of memristor processing modules,
• the plurality of memristor processing modules are configured to be capable of calculating under the dispatch and control of the first master control unit, and
• the plurality of memristor processing modules are further configured to be capable of communicating independently of the first master control unit to calculate to implement a computing task together;
• wherein the input interface is configured to receive an instruction to control an operation of the in-memory computing processor,
• the output interface is configured to output an operation result of the in-memory computing processor, and
• wherein each of the plurality of memristor processing modules comprises a plurality of memristor processing units, each of the plurality of memristor processing units comprises a memristor array, and the memristor array comprises a plurality of rows and columns of memristors arranged in an array;
• wherein the in-memory computing processor further comprises:
• a routing module and an input-output module,
• the routing module is configured to receive input data, parse the input data to obtain an input signal, and transmit the input signal to the input-output module,
• wherein the in-memory computing processor is configured to support a first computing mode, and in the first computing mode:
• the input-output module is configured to distribute and transmit the input signal to at least one memristor processing module of the plurality of memristor processing modules,
• the at least one memristor processing module is configured to calculate according to the input signal to obtain a first output signal,
• the input-output module is further configured to receive and collate the first output signal from the at least one memristor processing module to obtain first output data, and
• the routing module is further configured to output the first output data.