Arithmetic processing device and arithmetic method

An arithmetic processing method implemented by an arithmetic processing device, the arithmetic processing method comprising:

• obtaining a table configured to retain an approximate value D obtained by approximating a reciprocal 1/Y of a divisor Y for the each divisor Y in a predetermined range;
• calculating, by a first multiplier circuit of the arithmetic processing device, a product DY of the approximate value D that is output from the table and corresponds to the divisor Y and the divisor Y;
• comparing, by a dividend operation circuit of the arithmetic processing device, magnitude of a dividend X and magnitude of the divisor Y, and generating an operation value twice the dividend X in a case where the dividend X is smaller than the divisor Y, and generating the operation value equal to the dividend X in a case where the dividend X is equal to or larger than the divisor Y;
• calculating, a second multiplier circuit of the arithmetic processing device, a product of the approximate value D and the operation value as an initial value R(0) of a partial remainder R(n) where n denotes an iteration index indicating a current iteration number in a recursive calculation based on a recurrence formula;
• retaining, by a retaining circuit of the arithmetic processing device, the partial remainder R(n) in a retaining circuit;
• calculating, by a third multiplier circuit of the arithmetic processing device, a product DY*q(n) of the product DY and a partial quotient q(n) that is a value represented by upper k-bits of the partial remainder R(n) retained in the retaining circuit where k denotes a fixed value determined by a precision of the approximate value D;
• calculating, by a first addition circuit of the arithmetic processing device, a new partial remainder R(n+1) by subtracting the product DY*q(n) from the partial remainder R(n) retained in the retaining circuit and left-shifting a predetermined number of bits, and store the calculated new partial remainder R(n+1) in the retaining circuit;
• and
• arranging, by a quotient generation circuit of the arithmetic processing device, the partial quotient q(n) at a predetermined bit position of a quotient.