Efficient error signaling by memory

A host system, comprising:

• one or more interfaces comprising one or more signal paths operatable for communications with one or more memory systems;
• and
• processing circuitry coupled with the one or more interfaces and configured to cause the host system to:
• transmit a read command to a memory device;
• receive, from the memory device, first signaling indicating data associated with the read command;
• receive, from the memory device, second signaling comprising an indicator of a combination error having a first state, wherein the first state indicates a non-driven condition for the first signaling;
• and
• receive, from the memory device, third signaling comprising the indicator having the first state based at least in part on one or more errors in the data being detected by the memory device during an error control operation.

A method, comprising:

• performing, at a memory device and based at least in part on executing a read operation, an error control operation to detect one or more errors in data associated with the read operation;
• transmitting, to a host system, first signaling indicating the data associated with the read operation based at least in part on performing the error control operation;
• transmitting, to the host system, second signaling comprising an indicator of a combination error having a first state, wherein the first state indicates a non-driven condition for the first signaling;
• and
• transmitting, to the host system, third signaling comprising the indicator having the first state based at least in part on detecting the one or more errors in the data during the error control operation.