Address translation for accelerator-triggered memory access request

A hardware accelerator comprising:

• accelerator processing circuitry configurable, based on instructions executed by a processor, to perform a delegated task on behalf of the processing circuitry;
• control interface circuitry to exchange control signals with the processor;
• and
• memory access request circuitry to issue, to the processor via the control interface circuitry, an accelerator-triggered memory access request requesting access to a memory system;
• wherein the accelerator-triggered memory access request specifies a virtual address to be translated, by memory management circuitry associated with the processor, into a physical address of a memory system location to be accessed in response to the accelerator-triggered memory access request.

A method comprising:

• executing instructions using processing circuitry;
• in response to memory access instructions executed by the processing circuitry, performing address translation using memory management circuitry associated with the processing circuitry;
• via accelerator control interface circuitry, exchanging control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task;
• and
• in response to an accelerator-triggered memory access request received at the accelerator control interface circuitry from a given hardware accelerator, translating, using the memory management circuitry associated with the processing circuitry, a virtual address specified by the accelerator-triggered memory access request to a physical address of a memory system location to be accessed in response to the accelerator-triggered memory access request.

A non-transitory computer-readable storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising:

• processing program logic to execute instructions;
• memory management program logic associated with the processing program logic, to perform address translation in response to memory access instructions executed by the processing program logic;
• and
• accelerator control interface program logic to control at least one simulated hardware accelerator configurable, based on instructions executed by the processing program logic, to perform a delegated task;
• in which
• in response to an accelerator-triggered memory access request triggered by a given simulated hardware accelerator, the memory management circuitry associated with the processing program logic is configured to translate a virtual address specified by the accelerator-triggered memory access request to a simulated physical address of a memory system location to be accessed in response to the accelerator-triggered memory access request.