Low power and area optimized TM4 and TM5 compliant combination TMIO transmitter architecture
AssigneeSanDisk Technologies LLC
InventorsNiravkumar Natwarbhai Patel, Shiv Harit Mathur, Sumanth Reddy Rathna
Life of this patent
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Abstract
A system for altering an input/output (I/O) data signal of a NAND programming operation includes a skew-gen circuit comprising: a delay block coupled to an input of a two input logic OR gate, and a MUX logic gate coupled to an output of the logic OR gate. The skew-gen circuit is configured to: alter the pulse width of a input data signal by increasing the width of the data high signal and decreasing the width of the data low signal; and output the altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on the mode.
Claims17
A system for altering an input/output (I/O) data signal of a NAND programming operation, the system comprising:
- a skew-gen circuit comprising:
- a delay block coupled to an input of a two input logic OR gate, and a MUX logic gate coupled to an output of the logic OR gate and connected to a subsequent datapath, the skew-gen circuit configured to:
- alter a pulse width of a input data signal by increasing the width of a data high signal and decreasing a width of a data low signal;
- and
- output the altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on a NAND programming operation mode and provide an output to the subsequent datapath, the subsequent datapath coupling a pull-up predriver and pull-down predriver.
A system for altering an input/output (I/O) data signal of a NAND programming operation, the system comprising:
- a skew-gen circuit that supports both pseudo open drain (POD) and CTT signaling comprising:
- a delay block coupled to an input of a two input logic AND gate, and a MUX logic gate coupled to an output of the logic AND gate, the skew-gen circuit configured to:
- alter a pulse width of a input data signal by decreasing a width of a data high signal and increasing a width of a data low signal;
- and
- output the altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on a NAND programming operation mode.
A system for altering an input/output (I/O) data signal of a NAND programming operation, the system comprising:
- a skew-gen circuit comprising:
- a delay block coupled to an input of a programmable logic gate, the programmable logic gate programmable as either a logic AND gate for POD signaling or logic OR gate for LVSTL operation based on a control input applied to the skew-gen circuit, and a MUX logic gate coupled to an output of the programmable logic gate, the skew-gen circuit configured to:
- alter a pulse width of a input data signal by increasing or decreasing a width of a data high signal and decreasing or increasing a width of s data low signal based on the control input applied to the skew-gen circuit;
- and
- output an altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on a NAND programming operation mode.
Dependencies are inferred from the claim text.