Clock domain phase adjustment for memory operations

A device comprising:

• a physical memory communicatively coupled to a physical layer via a first clock domain;
• a memory controller communicatively coupled to the physical layer via a second clock domain;
• and
• a buffer implemented in the physical layer between the physical memory and the memory controller, the buffer configured to:
• detect a phase relationship of the first clock domain to the second clock domain;
• set a latency setting that specifies an amount of time between the memory controller issuing a memory operation involving data stored in the physical memory and output of the data from the buffer to the memory controller, wherein the latency setting is set using a phase adjustment generated based on the phase relationship, the phase adjustment generated based on a mismatch of the latency setting relative to an actual output, from the buffer, of the data involved in the memory operation;
• and
• align an edge of a clock signal in the first clock domain with an edge of a clock signal in the second domain by modifying the latency setting using the phase adjustment.

A method comprising:

• detecting a mismatch has occurred in data output by a buffer to a memory controller with respect to a latency setting used to control data output from the buffer, the buffer implemented in a physical layer that communicatively couples a first clock domain used by the memory controller with a second clock domain used by physical memory, the buffer between the physical memory and the memory controller, the latency setting specifying an amount of time between the memory controller issuing a memory operation involving data stored in the physical memory and output of the data from the buffer;
• setting a subsequent latency setting of the buffer based on a phase adjustment as a margin calculated between the latency setting and the data output, the phase adjustment based on a mismatch of the latency setting relative to an actual output, from the buffer, of the data involved in the memory operation;
• aligning an edge of a clock signal in the first clock domain with an edge of a clock signal in the second clock domain by modifying the latency setting using the phase adjustment;
• and
• controlling subsequent data output of the buffer to the memory controller based on the subsequent latency setting.