Memory device with computation function and operation method thereof

An operation method of a memory device with a computation function, the operation method comprising:

• loading an input operand comprising data that is operated on by a computation of the computation function;
• setting a plurality of column registers based on the input operand;
• performing a first internal read operation on memory cells of the memory device with respect to a first word line based on a plurality of first column compute selection signals respectively generated from the plurality of column registers;
• updating the plurality of column registers and an output register based on a result of the first internal read operation;
• and
• performing a second internal read operation on the memory cells of the memory device with respect to the first word line based on a plurality of second column compute selection signals respectively generated from the plurality of column registers that have been updated.

A memory device with a computation function, the memory device comprising:

• a first cell array configured to store a first computation output pattern;
• a first bit line sense amplifier configured to sense first voltages of first bit lines connected to the first cell array, and output the first voltages;
• a first column selection circuit configured to output a first output signal among the first voltages output by the first bit line sense amplifier based on a first column compute selection signal;
• a first column compute control circuit configured to generate the first column compute selection signal based on an input operand that comprises data that is operated on by a computation of the computation function;
• a second cell array configured to store a second computation output pattern;
• a second bit line sense amplifier configured to sense second voltages of second bit lines connected to the second cell array, and output the second voltages;
• and
• a second column selection circuit configured to output a second output signal among the second voltages output by the second bit line sense amplifier based on a second column compute selection signal,
• wherein, as an internal read operation on the first computation output pattern is repeatedly performed, the first column compute control circuit updates the first column compute selection signal,
• wherein the first column compute control circuit is configured to generate the second column compute selection signal based on the input operand, and
• wherein, as an internal read operation on both the first computation output pattern and the second computation output pattern is repeatedly performed, the first column compute control circuit updates the first column compute selection signal and the second column compute selection signal.