Touch display device
AssigneeLG Display Co., Ltd.
InventorsYoungsoo Lee, Jonghyun Han, YeonGyeong Bae
Life of this patent
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Abstract
A touch display device includes a touch planarization film. The touch planarization film may be disposed on an inclined portion of an encapsulation layer in a non-active area of a display panel, and a touch routing line may be disposed on the planarized area of the touch planarization film, so that it is possible to reduce parasitic capacitance between the touch routing line and a display signal line located under the encapsulation layer without increasing dimensions of the non-active area. Therefore, it is possible to easily adjust a width of the touch routing line and reduce the parasitic capacitance deviation between the touch routing lines, thereby improving the performance of the touch sensing.
Claims19
A touch display device comprising:
- a transistor over a substrate including an active area and a non-active area, including a first node electrode, a second node electrode, and a semiconductor layer in contact with the first node electrode and the second node electrode;
- a capacitor including a first electrode disposed on a same layer as a gate electrode of the transistor and a second electrode disposed over the first electrode;
- first and second planarization layers stacked over the transistor and the capacitor;
- a connection electrode disposed between the first planarization layer and the second planarization layer, and connected to the transistor;
- a light-emitting diode disposed over the second planarization layer at the active area;
- an encapsulation layer covering the light-emitting diode, and including a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked sequentially;
- at least one dam in the non-active area;
- a third planarization layer disposed over the encapsulation layer;
- a fourth planarization layer disposed over the third planarization layer;
- a plurality of touch electrodes disposed between the third planarization layer and the fourth planarization layer;
- and
- a display signal line disposed on a same layer as the semiconductor layer,
- wherein at least a portion of the third planarization layer is connected to the first inorganic encapsulation layer or the second inorganic encapsulation layer, and
- wherein at least a portion of the third planarization layer and at least a portion of the fourth planarization layer are overlapped with the at least one dam,
- wherein the third planarization layer includes a first inclined portion, and a second inclined portion steeper than the first inclined section,
- wherein the first inclined portion overlaps with the first planarization layer or the second planarization layer extended from the active area to the non-active area.
Dependencies are inferred from the claim text.