Hardware generation of 3D DMA configurations

A baseband processor for radar, comprising

• a fast Fourier transform (FFT) circuit including an FFT input and an FFT output;
• a first processing path having a first processing path input and a first processing path output, the first processing path including a memory coupled to the FFT output and the first processing path input via a first bus, and a Direct Memory Access (DMA) coupled between the memory and the first processing path output, the DMA coupled to the memory via a second bus, wherein the memory is configured to store the FFT output as a range-Doppler data cube;
• and
• a second processing path arranged in parallel with the first processing path, the second processing path including a detection circuit having a detection circuit input coupled to the FFT output and having a detection circuit output coupled to the DMA, the detection circuit configured to, in parallel with the storing of the FFT output as a range-Doppler data cube, receive the FFT output from the FFT circuit and output, to the DMA, a stream of bits indicating whether a value in the FFT output exceeds a threshold value;
• wherein the DMA is configured to
• generate a DMA read configuration for each bit in the second stream of bits indicating that the value exceeds the threshold value, the read configuration indicating a range and Doppler coordinate pair in the range-Doppler data cube that stores the value, and
• for each DMA read configuration, read a plurality of values from the range-Doppler data cube, wherein the plurality of values includes the value stored in the range-Doppler data cube at the range and Doppler coordinate pair indicated by the DMA read configuration.

A radar system, comprising:

• a radio frequency (RF) front end including a plurality of radar receive antennas, and an analog-to-digital converter to provide radar data;
• a signal processing unit coupled to the analog-to-digital converter, the signal processing unit configured to perform a first fast Fourier transform (FFT) on the radar data to provide a first FFT result;
• and further configured to perform a second FFT based on the first FFT result to thereby provide a second FFT result;
• a memory coupled to the signal processing unit and configured to store the second FFT result as a range-Doppler data cube;
• a detection circuit configured to receive the second FFT result from the signal processing unit, and output a second stream of bits based on the second FFT result, where individual bits in the second stream of bits indicate whether a value corresponding to a range and Doppler coordinate pair in the second FFT result exceeds a threshold value;
• and
• a Direct Memory Access (DMA) coupled to the memory and coupled to the detection circuit, the DMA configured to
• generate a DMA read configuration for each bit in the second stream of bits indicating that the value exceeds the threshold value, the read configuration indicating a range and Doppler coordinate pair in the range-Doppler data cube that stores the value, and
• for each DMA read configuration, to read a plurality of values from the range-Doppler data cube, wherein the plurality of values includes the value stored in the range-Doppler data cube at the range and Doppler coordinate pair indicated by the DMA read configuration.