US 12,584,242 B2Granted

Deformation compensation method for growing thick galium nitride on silicon substrate

AssigneeRobert Bosch GmbH

InventorsBo Cheng, Mordechai Kornbluth, Charles Tuffile, Jens Baringhaus, Christian Huber

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Abstract

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and AlxGa(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO2, SiCxN(1-x), SiN, SiCxO(1-x), SiC, SiNxO(1-x), Al2O3, and/or Cr2O3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

Claims17

Dependent claims

A method of manufacturing a structure, comprising the steps of:

applying a semiconductor layer to a substrate;
the semiconductor layer being formed of gallium nitride (GaN), and the substrate being formed of a silicon-based material;
applying at least one deformation compensation layer to the substrate opposite the semiconductor layer;
the at least one deformation compensation layer being formed of at least one of SiO2, SiCxN(1-x), SiN, SiCxO(1-x), SiC, SiNxO(1-x), Al2O3, and Cr2O3, wherein 0<x<1;
estimating at least one of (a) an epitaxial growth stress, (b) an interface stress, and (c) a thermal stress of the substrate and each of the semiconductor layer and the at least one deformation compensation layer at a selected temperature and a selected thickness before, during, or after the steps of applying the semiconductor layer and applying at least one deformation compensation layer;
and
determining the temperature at which the semiconductor layer and the at least one deformation compensation layer will be applied and/or the thickness of the semiconductor layer and the at least one deformation compensation layer to be applied based on at least one of the estimated epitaxial growth stress, the estimated interface stress, and the estimated thermal stress;
wherein the estimated thermal stress is determined by applying the following equations for each of the substrate, the semiconductor layer, and the at least one deformation compensation layer:
{
ε
}
=
[
D
]
-
1
⁢
{
σ
}
+
{
ε
th
}
,
{
ε
th
}
=
a
e
×
Δ
⁢
T
=
a
e
(
T
-
T
ref
)
,
and
⁢
{
σ
}
=
[
D
]
⁢
{
ε
}
,
where {ε} is overall strain, {εth} is thermal strain, αe is a material coefficient of thermal expansion (CTE), T is a selected temperature, Tref is a reference temperature, [D] is a strain-stress matrix, and {σ} is a stress matrix.

60 more elements

Dependencies are inferred from the claim text.