Inter-poly connection for parasitic capacitor and die size improvement

A micro-electromechanical system (MEMS) structure, comprising:

• one or more semiconductor devices arranged on or within a substrate;
• a MEMS substrate having an ambulatory element, wherein the MEMS substrate is connected to the substrate by a conductive bonding structure;
• one or more conductive polysilicon vias extending from the conductive bonding structure completely through the MEMS substrate to protrude outward from a first surface of the MEMS substrate facing away from the substrate;
• a capping substrate separated from the substrate by the MEMS substrate and having sidewalls forming one or more recesses within a surface of the capping substrate facing the MEMS substrate;
• a dielectric layer between the MEMS substrate and the capping substrate, wherein the one or more conductive polysilicon vias extend through the dielectric layer;
• and
• wherein the conductive bonding structure comprises a polysilicon layer and a metal layer, the polysilicon layer laterally extending past opposing outermost sidewalls of the one or more conductive polysilicon vias and having an upper surface that physically contacts a lower surface of the one or more conductive polysilicon vias.

A micro-electromechanical system (MEMS) structure, comprising:

• one or more semiconductor devices arranged on a substrate, wherein the substrate comprises one or more conductive interconnects;
• a MEMS substrate having an ambulatory element, wherein a front-side of the MEMS substrate is connected to the substrate by a conductive bonding structure, the conductive bonding structure being coupled to the one or more conductive interconnects;
• a capping substrate connected to the MEMS substrate, wherein the MEMS substrate is between the substrate and the capping substrate;
• and
• one or more conductive polysilicon vias extending from a surface of the conductive bonding structure, through the MEMS substrate, and to the capping substrate, wherein the one or more conductive polysilicon vias comprise one or more interior surfaces forming a void, the void being vertically outside of the capping substrate and having a width that varies over a height of the void.