Semiconductor package including pads

A semiconductor package comprising:

• a first semiconductor chip including a first substrate, a plurality of first pads on the first substrate, and a first insulating layer at least partially surrounding the plurality of first pads;
• and
• a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second pads below the second substrate and in contact with the plurality of first pads, and a second insulating layer at least partially surrounding the plurality of second pads and in contact with the first insulating layer,
• wherein at least one of the plurality of first pads includes a base layer including a recess, an outer barrier layer extending along a side surface and a lower surface of the base layer, at least one conductive pattern layer and at least one insulating pattern layer alternately disposed in the recess, and an inner barrier layer extending along a side surface and a lower surface of the at least one conductive pattern layer, and includes an upper surface defined by the base layer, the outer barrier layer, the at least one conductive pattern layer, the inner barrier layer, and the at least one insulating pattern layer.

A semiconductor package comprising:

• a first semiconductor chip including a first substrate, a plurality of first pads on the first substrate, a first insulating layer surrounding side surfaces of the plurality of first pads, and a plurality of through-electrodes passing through the first substrate and connected to the plurality of first pads;
• and
• a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second pads below the second substrate and in contact with the plurality of first pads, and a second insulating layer surrounding side surfaces of the plurality of second pads and in contact with the first insulating layer,
• wherein at least one of the plurality of first pads includes a base layer including a recess and an outer wall surrounding the recess, and a conductive pattern layer and an insulating pattern layer in the recess, and
• an uppermost surface of the outer wall of the base layer and an uppermost surface of the conductive pattern layer are in contact with at least one of the plurality of second pads.