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US 12,582,006 B2Granted
Discrete three-dimensional processor
AssigneeHong Kong HaiCun Technology Co., Limited
InventorGuobiao Zhang
Life of this patent
Estimating the term…
Abstract
A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises memory arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the memory arrays. The first and second dice have substantially different structures, more particularly back-end-of-line (BEOL) structures.
Claims56
A discrete three-dimensional (3-D) processor, comprising:
- a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a memory array and an off-die peripheral-circuit component thereof, wherein:
- said memory array comprises 3-D structures;
- said non-memory circuit and said off-die peripheral-circuit component are both 2-D circuits;
- said non-memory circuit is not a part of any memory;
- and,
- said non-memory circuit is communicatively coupled with said memory array through said off-die peripheral-circuit component;
- a first die comprising the memory arrays of said plurality of SPU's;
- a second die comprising the non-memory circuits and the off-die peripheral-circuit components of the memory arrays of said plurality of SPU's;
- a plurality of inter-die connections communicatively coupling said first and second dice;
- wherein said off-die peripheral-circuit component comprises at least a portion of an address decoder of said memory array;
- and, said first and second dice have different back-end-of-line (BEOL) structures.
8 more elements
A discrete three-dimensional (3-D) processor, comprising:
- a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a memory array and an off-die peripheral-circuit component thereof, wherein:
- said memory array comprises 3-D structures;
- said non-memory circuit and said off-die peripheral-circuit component are both 2-D circuits;
- said non-memory circuit is not a part of any memory;
- and,
- said non-memory circuit is communicatively coupled with said memory array through said off-die peripheral-circuit component;
- a first die comprising the memory arrays of said plurality of SPU's;
- a second die comprising the non-memory circuits and the off-die peripheral-circuit components of the memory arrays of said plurality of SPU's;
- a plurality of inter-die connections communicatively coupling said first and second dice;
- wherein said off-die peripheral-circuit component comprises at least a portion of a sense amplifier of said memory array;
- and, said first and second dice have different back-end-of-line (BEOL) structures.
8 more elements
A discrete three-dimensional (3-D) processor, comprising:
- a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a memory array and an off-die peripheral-circuit component thereof, wherein:
- said memory array comprises 3-D structures;
- said non-memory circuit and said off-die peripheral-circuit component are both 2-D circuits;
- said non-memory circuit is not a part of any memory;
- and,
- said non-memory circuit is communicatively coupled with said memory array through said off-die peripheral-circuit component;
- a first die comprising the memory arrays of said plurality of SPU's;
- a second die comprising the non-memory circuits and the off-die peripheral-circuit components of the memory arrays of said plurality of SPU's;
- a plurality of inter-die connections communicatively coupling said first and second dice;
- wherein said off-die peripheral-circuit component comprises at least a portion of a programming circuit of said memory array;
- and, said first and second dice have different back-end-of-line (BEOL) structures.
8 more elements
A discrete three-dimensional (3-D) processor, comprising:
- a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a memory array and an off-die peripheral-circuit component thereof, wherein:
- said memory array comprises 3-D structures;
- said non-memory circuit and said off-die peripheral-circuit component are both 2-D circuits;
- said non-memory circuit is not a part of any memory;
- and,
- said non-memory circuit is communicatively coupled with said memory array through said off-die peripheral-circuit component;
- a first die comprising the memory arrays of said plurality of SPU's;
- a second die comprising the non-memory circuits and the off-die peripheral-circuit components of the memory arrays of said plurality of SPU's;
- a plurality of inter-die connections communicatively coupling said first and second dice;
- wherein said off-die peripheral-circuit component comprises at least a portion of a charge-pump circuit for said memory array;
- and, said first and second dice have different back-end-of-line (BEOL) structures.
8 more elements
Dependencies are inferred from the claim text.