Semiconductor device including impurity regions and element isolation portion and method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorsYudai Higa, Atsushi Sakai, Yotaro Goto
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AssigneeRenesas Electronics Corporation
InventorsYudai Higa, Atsushi Sakai, Yotaro Goto
Estimating the term…
A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.
A semiconductor device including a cell region in which Metal Insulator Semiconductor Field Effect Transistors (MISFETs) are formed and a peripheral region surrounding the cell region in a plan view, comprising:
A method of manufacturing a semiconductor device including a cell region in which Metal Insulator Semiconductor Field Effect Transistors (MISFETs) are formed and a peripheral region surrounding the cell region in a plan view, the method comprising:
Dependencies are inferred from the claim text.