Semiconductor memory devices

A semiconductor memory device comprising;

• a substrate;
• a first conductive line extending in a first horizontal direction parallel to an upper surface of the substrate, on the substrate;
• a first electrode on the first conductive line;
• an information storage pattern on the first electrode;
• a second electrode on the information storage pattern;
• a second conductive line extending in a second horizontal direction parallel to the upper surface of the substrate, on the second electrode;
• a first sub-spacer on a side wall of the information storage pattern, a side wall of the second electrode, and an upper surface of the first electrode;
• and
• a second sub-spacer on the first sub-spacer,
• wherein a surface area of the upper surface of the first electrode is greater than a surface area of a bottom surface of the information storage pattern,
• wherein a surface area of a bottom surface of the second electrode is greater than a surface area of an upper surface of the information storage pattern,
• wherein the first and second sub-spacers include different materials from each other, and
• wherein the first electrode is free of having contact with the second sub-spacer.

A semiconductor memory device comprising:

• a substrate;
• a first conductive line extending in a first horizontal direction parallel to an upper surface of the substrate, on the substrate;
• a first memory cell on the first conductive line, wherein the first memory cell comprises a first electrode on the first conductive line, a first information storage pattern on the first electrode, and a second electrode on the first information storage pattern;
• a second conductive extending in a second horizontal direction parallel to the upper surface of the substrate, on the second electrode;
• a first spacer on a side wall of the first memory cell;
• a third conductive line extending in the first horizontal direction, on the second electrode;
• a second memory cell on the third conductive line, wherein the second memory cell comprises a third electrode on the third conductive line, a second information storage pattern on the third electrode, and a fourth electrode on the second information storage pattern;
• and
• a second spacer on a side wall of the second memory cell,
• wherein a side wall of the first electrode is free of having the first spacer thereon,
• wherein a width of an upper surface of the first electrode in the first horizontal direction is greater than a width of a bottom surface of the first information storage pattern in the first horizontal direction,
• wherein a side wall of the third electrode is free of having the second spacer thereon,
• wherein a width of an upper surface of the third electrode in the first horizontal direction is greater than a width of a bottom surface of the second information storage pattern in the first horizontal direction, and
• wherein the first spacer includes a first sub-spacer and a second sub-spacer, the second spacer includes a third sub-spacer and a fourth sub-spacer, the first sub-spacer and the third sub-spacer each include a first insulating material, and the second sub-spacer and the fourth sub-spacer each include a second insulating material different from the first insulating material.