Stress absorbing trench capacitor and method for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorFu-Chiang Kuo
Life of this patent
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Abstract
The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a trench with a predetermined aspect ratio in the substrate to form two fins, wherein the forming of the trench induces the substrate to warp toward a first direction; forming a metal-insulator-metal (MIM) stack on sidewalls of the two fins in the trench, and leaving a space surrounded by the MIM stack in the trench; determining whether the substrate warps toward a second direction reverse to the first direction after the forming of the MIM stack; and in response to the substrate warping toward the second direction, depositing an insulating layer to cover an upper surface of the MIM stack and seal the trench to thereby leave a void in the space.
Claims20
A method of manufacturing a semiconductor structure, comprising:
- providing a substrate;
- forming a trench with a predetermined aspect ratio in the substrate to form two fins, wherein the forming of the trench induces the substrate to warp toward a first direction;
- forming a liner layer to cover the substrate and the two fins, wherein the liner layer has different widths at different heights of the two fins, resulting in sidewalls of the liner layer within the trench being parallel to each other;
- forming a metal-insulator-metal (MIM) stack on the sidewalls of the liner layer that are on the two fins in the trench, and leaving a space surrounded by the MIM stack in the trench;
- determining whether the substrate warps toward a second direction reverse to the first direction after the forming of the MIM stack;
- and
- depositing an insulating layer to cover an upper surface of the MIM stack and seal the trench, thereby leaving a void in the space, wherein an amount of the insulating layer is associated with a warpage level of the substrate.
A method of manufacturing a semiconductor structure, comprising:
- providing a substrate;
- forming two fins separated by etching a trench with a predetermined aspect ratio in the substrate;
- forming a liner layer to cover the substrate and the two fins, wherein the liner layer has different widths at different heights of the two fins, resulting in sidewalls of the liner layer within the trench being parallel to each other on the two fins;
- forming a capacitor on the sidewalls of the liner layer that are on the two fins, and leaving a space surrounded by the capacitor between the two fins;
- determining a warpage level of the substrate;
- and
- depositing an insulating layer over the capacitor and the trench to seal the space and leave a void in the trench, wherein a thickness of the insulating layer in the trench is associated with the warpage level of the substrate.
A semiconductor structure, comprising:
- a substrate;
- two fins separated to each other by a trench in the substrate;
- a liner layer continuously on the substrate and the two fins, wherein the liner layer has different widths at different heights of the two fins, resulting in sidewalls of the liner layer within the trench being parallel to each other;
- a first conductive layer on the liner layer over the substrate and sidewalls of the two fins;
- a dielectric layer on the first conductive layer;
- a second conductive layer on the dielectric layer;
- and
- an insulating layer covering a top portion and sidewalls of the second conductive layer in the trench, wherein
- the insulating layer includes a void within the insulating layer, wherein the void has a first width proximal to adjacent upper corners of the two fins less than a second width proximal to a bottom of the fins.
Dependencies are inferred from the claim text.