Comparator and image sensor including the same

An image sensor comprising:

• a pixel array comprising a plurality of pixels;
• a ramp generator configured to generate a ramp signal;
• and
• an analog-digital conversion circuit configured to convert a pixel signal, which is output from the pixel array, into a digital signal, the analog-digital conversion circuit comprising a comparator and a counter,
• wherein the comparator comprises:
• a first input transistor comprising a gate configured to receive the ramp signal;
• a second input transistor comprising a gate configured to receive the pixel signal;
• a first load transistor connected to a source or drain of the first input transistor;
• a second load transistor connected to a source or drain of the second input transistor;
• a first shift transistor comprising a gate connected to the gate of the first input transistor and connected to a source or drain of the first load transistor;
• and
• a second shift transistor comprising a gate connected to the gate of the second input transistor and connected to a source or drain of the second load transistor,
• the first load transistor and the first shift transistor are configured to be selectively driven according to a first switching signal and a second switching signal, respectively, and
• the second load transistor and the second shift transistor are configured to be selectively driven according to the first switching signal and the second switching signal, respectively.

A comparator comprising:

• a first input transistor comprising a gate connected to a first input node;
• a second input transistor comprising a gate connected to a second input node;
• a first load transistor comprising a drain connected to a drain of the first input transistor;
• a second load transistor comprising a drain connected to a drain of the second input transistor;
• a first shift transistor comprising a drain connected to the drain of the first input transistor;
• a second shift transistor comprising a drain connected to the drain of the second input transistor;
• a first top switch connected to the first load transistor in series;
• a second top switch connected to the second load transistor in series;
• a first bottom switch connected to the first shift transistor in series;
• and
• a second bottom switch connected to the second shift transistor in series.