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US 12,580,679 B1Granted
Q Margin
OwnerYue Pan, Jonas Geyerinventors
Life of this patent
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Abstract
A method, system, and ASIC chip for comparing a bit error rate (BER) to a forward error correction (FEC) threshold to determine a Q margin for a codeblock; wherein the BER corresponds to the number of errors in a given amount of data; where a codeblock of a FEC corresponds to the given amount of data; wherein the FEC threshold corresponds to the maximum amount of errors per codeblock that the FEC is able to remove per given amount of data; wherein the Q margin corresponds to a difference between the BER and the FEC threshold.
Claims20
A method, comprising:
- receiving a plurality of forward error correction (FEC) codeblocks, wherein each FEC codeblock of the plurality of FEC codeblocks corresponds to a different portion of a transmission, and wherein each FEC codeblock defines a bit error rate (BER) corresponding to an amount of errors in the different portion of the transmission;
- determining a maximum BER of the plurality of FEC codeblocks;
- determining a Q margin for the transmission by comparing the maximum BER with a FEC threshold, wherein the FEC threshold corresponds to a maximum amount of errors per FEC codeblock that a forward error corrector is capable of correcting;
- and
- determining if the transmission comprises an acceptable amount of errors or an unacceptable amount of errors based on the Q margin.
2 more elements
An application-specific integrated circuit (ASIC) chip, comprising:
- a forward error corrector;
- and
- logic enabling:
- receiving a plurality of forward error correction (FEC) codeblocks, wherein each FEC codeblock of the plurality of FEC codeblocks corresponds to a different portion of a transmission, and wherein each FEC codeblock defines a bit error rate (BER) corresponding to an amount of errors in the different portion of the transmission;
- determining a maximum BER of the plurality of FEC codeblocks;
- determining a Q margin for the transmission by comparing the maximum BER with a FEC threshold, wherein the FEC threshold corresponds to a maximum amount of errors per FEC codeblock that the forward error corrector is capable of correcting;
- and
- determining if the transmission comprises an acceptable amount of errors or an unacceptable amount of errors based on the Q margin.
5 more elements
A system, comprising:
- a first transceiver comprising a first application-specific integrated circuit (ASIC) chip and a first forward error correction (FEC) element of a forward error corrector;
- a second transceiver comprising a second ASIC chip and a second FEC element of the forward error corrector;
- and
- logic enabling:
- receiving a plurality of forward error correction (FEC) codeblocks, wherein each FEC codeblock of the plurality of FEC codeblocks corresponds to a different portion of a transmission, and wherein each FEC codeblock defines a bit error rate (BER) corresponding to an amount of errors in the different portion of the transmission;
- determining a maximum BER of the plurality of FEC codeblocks;
- determining a Q margin for the transmission by comparing the maximum BER with a FEC threshold, wherein the FEC threshold corresponds to a maximum amount of errors per FEC codeblock that a forward error corrector is capable of correcting;
- and
- determining if the transmission comprises an acceptable amount of errors or an unacceptable amount of errors based on the Q margin.
6 more elements
Dependencies are inferred from the claim text.