US 12,580,604 B2Granted

Multi-stage digital converters

AssigneeEvertz Microsystems Ltd.

InventorsJeff Wei, Eric Fankhauser, Xiaobing Sun

Life of this patent

Estimating the term…

Loading patent…

Abstract

The present disclosure generally relates to multi-stage digital converters, including multi-stage digital down-converters (DDCs) and multi-stage digital up-converters (DUCs). In at least one example, the multi-stage digital down converter (DDC) comprises a plurality of stages, each stage comprising a frequency mixer and a decimation filter, and at least one controller coupled to one or more of the plurality of stages and operable to control one of the frequency mixer and decimation filter. In another example, the multi-stage digital up converter (DUC) comprises a plurality of stages, each stage comprising a frequency mixer and interpolation filter; at least one controller coupled to one or more of the plurality of stages and operable to control one of the frequency mixer and the interpolation filter.

Claims18

Dependent claims

A multi-stage digital down converter (DDC) comprising:

a plurality of receiving stages, including a first receiving stage for receiving an input signal, a plurality of last receiving stages wherein each of the plurality of receiving stages is for transmitting a respective output signal, and one or more mid-receiving stages coupled in series between the first receiving stage and each of the last receiving stages in a fan-out architecture having a plurality of receiving signal paths, wherein:
each of the receiving stages has a decimation filter having a corresponding receiving stage decimation ratio to progressively decimate the sampling rate of the input signal;
at least one of the receiving stages has a controllable receiving stage decimation ratio;
and
each receiving signal path extending from the first receiving stage to one of the last receiving stages, and wherein each receiving signal path has a selected overall decimation ratio corresponding to the receiving stage decimation ratios of the receiving stages in that receiving signal path;
and
a controller coupled to each of the receiving stages having a controllable decimation ratio to control an overall decimation ratio of the DDC.

4 more elements

A multi-stage digital up converter (DUC) comprising:

a plurality of transmitting stages, including a plurality of first transmitting stages wherein each of the first transmitting stages is for receiving a respective input signal, a last transmitting stage for transmitting an output signal, and one or more mid-transmitting stages coupled in series between each of the first transmitting stages and the last transmitting stage in a fan-in architecture having a plurality of transmitting signal paths, wherein:
each of the transmitting stages has an interpolation filter having a corresponding transmitting stage up-sampling ratio to progressively up-sample the sampling rate of the respective input signal;
at least one of the transmitting stages has a controllable transmitting stage interpolation ratio;
and
each transmitting signal path extending from one of the first transmitting stages to the last transmitting stage, and wherein each transmitting signal path has a selected overall up-sampling ratio corresponding to the transmitting stage up-sampling ratios of the transmitting stages in that transmitting signal path;
and
a controller coupled to each of the transmitting stages having a controllable transmitting stage up-sampling ratio to control an overall up-sampling ratio of the DUC.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/322,008Filed 23 May 2023 · us provisional application
Priority: 24 May 2022
Published: US 2023/0387959 A130 Nov 2023
Granted: 17 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H04B 1/406
Using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency: with more than one…
H04B 1/0017
Wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage: digital filtering
H04B 1/0021
Wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage: decimation, i.e. data rate reduction techniques
H04B
Transmission