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US 12,580,599 B2Granted
Variable delay FIR filter for reflection equalization
AssigneeTexas Instruments Incorporated
InventorRobert C. Keller
Life of this patent
Estimating the term…
Abstract
In an example, a circuit includes a first signal path including a first filter having a first number of taps and having an input and an output. The circuit also includes a combiner having first and second inputs, the first input coupled to the output of the first filter. The circuit includes a second signal path coupled to the input of the first filter and to the second input of the combiner. The second signal path includes a gain component, a delay component coupled to the gain component, and a second filter having a second number of taps and coupled to the delay component.
Claims26
A circuit comprising:
- a first signal path including a first filter having a first number of taps and having an input and an output;
- a combiner having first and second inputs, the first input coupled to the output of the first filter;
- and
- a second signal path coupled to the input of the first filter and to the second input of the combiner, the second signal path including:
- a gain component configured to provide a less than unity gain;
- a delay component coupled to the gain component;
- and
- a second filter having a second number of taps and coupled to the delay component, wherein the second number of taps is responsive to the less than unity gain.
5 more elements
A circuit comprising:
- a first filter having a first number of taps and having an input and an output;
- a combiner having first and second inputs, the first input coupled to the output of the first filter;
- a gain component having an input coupled to the input of the first filter and having an output, the gain component configured to provide a less than unity gain;
- a second filter having a second number of taps, wherein the second number of taps is responsive to the less than unity gain;
- a delay component having an input coupled to the output of the gain component and having an output, wherein the second filter has an input coupled to the output of the delay component, and wherein the second filter has an output coupled to the second input of the combiner;
- and
- a digital-to-analog converter having an input coupled to an output of the combiner.
4 more elements
A circuit comprising:
- a first filter having a first number of taps and having an input and an output;
- a combiner having first and second inputs, the first input coupled to the output of the first filter;
- a delay component having an input and an output;
- a gain component having an input coupled to the output of the delay component and having an output coupled to the second input of the combiner, the gain component configured to provide a less than unity gain;
- a second filter having a second number of taps and having an input coupled to the input of the first filter and having an output coupled to the input of the delay component, wherein the second number of taps is responsive to the less than unity gain;
- and
- an analog-to-digital converter having an output coupled to the input of the first filter.
4 more elements
A circuit, comprising:
- a first filter having a first number of taps and having an input and an output;
- a first combiner having first and second inputs, the first input coupled to the output of the first filter;
- a first gain component having an input coupled to the input of the first filter and having an output, the first gain component configured to provide a less than unity gain;
- a second filter having a second number of taps, wherein the second number of taps is responsive to the less than unity gain;
- a first delay component having an input coupled to the output of the first gain component and having an output, wherein the second filter has an input coupled to the output of the first delay component, and wherein the second filter has an output coupled to the second input of the first combiner;
- a digital-to-analog converter having an input coupled to an output of the first combiner;
- a third filter having a third number of taps and having an input and an output;
- a second combiner having first and second inputs, the first input coupled to the output of the third filter;
- a fourth filter having a fourth number of taps and having an input coupled to the input of the third filter and having an output;
- a second delay component having an input coupled to the output of the fourth filter and having an output;
- a second gain component having an input coupled to the output of the second delay component and having an output coupled to the second input of the second combiner;
- and
- an analog-to-digital converter having an output coupled to the input of the third filter.
10 more elements
Dependencies are inferred from the claim text.